Various analog sampling rate conversion schemes that utilize a resampling approach are known in the art. Typically, a first (forward) digital-to-analog converter (DAC1) converts input data x.sub.1 (k) to an analog form at a rate f.sub.1, a sample clock rate of x.sub.1 (k). An output of DAC1 is then passed through a low-pass filter (LPF1) to remove high frequency components, the output of the LPF1 further being sent to a first analog-to-digital converter (ADC1) and sampled at a second rate f.sub.2, thereby generating digital samples y.sub.1 (n).
An inverse converter almost identical to the forward converter, typically a second digital-to-analog converter (DAC2), converts a digital sample sequence y.sub.2 (n) that is synchronous with y.sub.1 (n) to an analog form at a clock rate of f.sub.2. An output of DAC2 is generally passed through a second low-pass filter (LPF2), and the output of that LPF2 is converted by a second analog-to-digital converter (ADC2) to a digital sequence x.sub.2 (k) at a rate of f.sub.1. Where ADC2 is controlled by the same clock of x.sub.1 (k), the ADC1 and DAC2 are operated with a clock that is synchronous with the sample clock, sequences x.sub.1 (k) and x.sub.2 (k) are synchronous, and rate conversion is linear and time-invariant.
It has been shown that an analog rate converter substantially comprising a DAC-LPF-ADC may be realized digitally. Hence, a pair of digital rate converters may be utilized to form forward-inverse rate conversion, allowing reduction of the number of required analog components and concomitant costs for rate conversion devices.
However, since accuracy of input/output sampling rates and conversion ratios may vary with time and accuracy of digital number representations typically involve at least some degree of imprecision, exact synchronization between x.sub.1 (k) and x.sub.2 (k) in sampling timing is typically a problem where digital rate converters are implemented.